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toshiba toshiba corporation 1/14 tlcs-90 tmp90 TMP90PH02 the information contained here is subject to change without notice. the information contained herein is presented only as guide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others. these toshiba products are intended for usage in general electronic equipments (of?e equipment, communication equipment, measuring equipment, domestic electri?ation, etc.) please make sure that you consult with us before you use these toshiba products in equip- ments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traf? signal, combustion control, all types of safety devices, etc.). toshiba cannot accept liability to any damage which may occur in case these toshiba products were used in the mentioned equipments without prior consultation with toshiba. cmos 8?it microcontrollers TMP90PH02p/TMP90PH02m 1. outline and characteristics the TMP90PH02 is a system evaluation lsi having a built in one-time prom for tmp90ch02. a programming and veri?ation for internal prom is achieved by using a general eprom programmer with an adapter socket. the function of this device is exactly same as the tmp90ch02 and tmp90c802a by programming to the inter- nal prom. the differenes between TMP90PH02 and tmp90c802a are the internal ram size, and the internal prom size. the following are the memory map of TMP90PH02 and tmp90c802a. parts no. rom ram package adapter socket no. TMP90PH02p otp 16384 x 8bit 512 x 8bit 40-dip bm1158 TMP90PH02m 40-sop bm1159 www.datasheet.in
2/14 toshiba corporation TMP90PH02 figure 1. TMP90PH02 block diagram www.datasheet.in
toshiba corporation 3/14 TMP90PH02 2. pin assignment and functions the assignment of input/output pins, their names and functions are described below. 2.1 pin assignment figure 2.1 (1) shows pin assignment of the TMP90PH02. figure 2.1 (1). pin assignment www.datasheet.in
4/14 toshiba corporation TMP90PH02 2.2 pin names and functions the TMP90PH02p has mcu mode and prom mode. (1) mcu mode (the TMP90PH02 and the tmp90c802a are pin compatible). table 2.2 pin names and functions pin name no. of pins i/o 3 states function p00 ~ p07 /d0 ~ d7 8 i/o port 0: 8-bit i/o port that allows selection of input/output on byte basis 3 states data bus: also functions as 8-bit bidirectional data bus for external memory p10 ~ p17 /a0 ~ a7 8 i/o port 1: 8-bit i/o port that allows selection on byte basis output addrress bus: the lower 8 bits address bus for external memory p20 ~ p27 /a8 ~ a 15 8 i/o port 2: 8-bit i/o port that allows selection on byte basis output addrress bus: the uppper 8 bits address bus for external memory p31 /rxd 1 input port 31: 1-bit input port receives serial data p32 /txd /r ts /sclk 1 output port 32: 1-bit output port serial clock output p33 /txd 1 output port 33: 1-bit output port transmits serial data p35 /rd 1 output port 35: 1-bit output port read: generates strobe signal for reading external memory p36 /wr 1 output port 36: 1-bit output port writes: generates strobe signal for writing external memory p37 /w ait to1 1 input port 37: 1-bit input port wait: input pin for connecting slow speed memory or peripheral lsi output timer output 1: output of timer 0 or 1 p80 /into 1 input port 80: 1-bit input port interrupt request pin 0: interrupt request pin (level/rising edge is programmable) p81 /int1 /ti4 1 input port 81: 1-bit input port interrupt request pin 1: interrupt request pin (rising/falling edge is programmable) timer input 2: counter/capture trigger signal for timer 2 nmi 1 input non-maskable interrupt request pin: falling edge interrupt request pin clk 1 output clock output: generates clock pulse at 1/4 frequency of clock oscillation. it is pulled up internally during resetting. ea 1 input connects with v cc pin . reset 1 input reset: initializes the TMP90PH02 (built-in pull-up resistor) x1/x2 2 input/ output pin for quartz crystal or ceramic resonator (1 ~ 16.0mhz) v cc 1 power supply (+5v) v ss (gnd) 1 ground (0v) www.datasheet.in
toshiba corporation 5/14 TMP90PH02 2) prom mode table 2.2.2 pin function name no. of pins i/o function pin name (mcu mode) a7 ~ a0 8 input address input p17 ~ p10 p24 ~ p20 a12 ~ a8 5 input a15 ~ a13 3 input be fixed to ??level. p27 ~ p25 d7 ~ d0 8 i/0 data input/output p07 ~ p00 oe 1 input output enable input p35 ce 1 input chip enable input p36 vpp 1 power supply 12.5v/5v (programming power supply) ea vcc 1 power supply 5v vss 1 power supply 0v pin name no. of pins i/o pin setting p31 1 input be fixed level. p32 ~ p34 3 output open p37 1 input be fixed level. p80 , p81 2 input be fixed to ??level. nmi 1 input be fixed to level. reset 1 input be fixed to ??level. clk 1 input be fixed to ??level. x1 1 input resonator connection pin x2 1 output www.datasheet.in
6/14 toshiba corporation TMP90PH02 3. operation the TMP90PH02 is the otp version of the tmp90ch02 that is replaced an internal rom from mask rom to eprom. the function of TMP90PH02 is exactly same as that of tmp90c802a. refer to the tmp90ch02 except the functions which are not described this section. the following is an explanation of the hardware con?uration and operation in the relation to the TMP90PH02. the TMP90PH02 has an mcu mode and a prom mode. 3.1 mcu mode (1) mode setting and function the mcu mode is set by opening the clk pin (output status). in the mcu mode, the operation is the same as that of tmp90ch02. (2) memory map figure 3.1 shows the memory map of TMP90PH02, and the accessing area by the respective address- ing mode. figure 3.1. TMP90PH02 memory map www.datasheet.in
toshiba corporation 7/14 TMP90PH02 3.2 prom mode (1) mode setting and function prom mode is set by setting the reset and clk pins to the ??level. the programming and veri?ation for the internal prom is achieved by using a general prom programmer with the adaptor socket. the device selection (rom type) should be ?7256?with following conditions. size : 256kbit (32k x 8-bit) vpp: 12.5v tpw: 1ms figure 3.2 shows the setting of pins in prom mode. figure 3.2. prom mode pin setting (2) programming flow chart the programming mode is set by applying 12.5v (programming voltage) to the vpp pin when the following pins are set as follows, (vcc : 6.0v) *these conditions can be ( reset : ??level) obtained by using adaptor (clk : ??level) socket. after the address and data have been ?ed, a data on the data bus is programmed when the ce pin is set to ?ow?(1ms plus is required). general programming procedure of an eprom program- mer is as follows, ?write a data to a speci?d address for 1ms. ?verify the data. if the read-out data does not match the expected data, another writing is performed until the correct data is written (max. 25 times). after the correct data is written, an additional writing is performed by using three times longer programming pulse width (1ms x programming times), or using three times more programming pulse number. then, verify the data and increment the address. the veri?ation for all data is done under the condition of vpp = vcc = 5v after all data were written. figure 3.3 shows the programming ?w chart. www.datasheet.in
8/14 toshiba corporation TMP90PH02 figure 3.1. TMP90PH02 memory map (3) the security bit the TMP90PH02 has the security bit in prom cell. if the sercuity bit is programmed to ?? the content of the prom is disable to read in prom mode. how to program the security bit. 1) connect a15 pins to v cc . [otherwise connect them to gnd to program prom] 2) set programming address to 0000h. 3) to program the security bit, set d0 to ?? 4) set d2 ~ d7 to ??respectively. the following table shows the 8-bit data to program the security bit. table 3.1 data to program bit to program d0 ~ d7 a0 ~ a13 a14, a15 the security bit feh all ? a14 = ? a15 = ? prom (0000h ~ 3fffh) all ? www.datasheet.in
toshiba corporation 9/14 TMP90PH02 4. electrical characteristics TMP90PH02p/TMP90PH02m note: i dar is guaranteed for a total of up to 8 optional ports. 4.1 absolute maximum ratings symbol parameter rating unit v cc supply voltage -0.5 ~ + 7 v v in input voltage -0.5 ~ v cc + 0.5 v p d power dissipation (ta = 85 c) 250 mw t solder soldering temperature (10s) 260 c t stg storage temperature -65 ~ 150 c t opr operating temperature -40 ~ 85 c 4.2 dc characteristics v cc = 5v 10% ta = -40 ~ 85 c (1 ~ 10mhz) ta = -20 ~ 70 (1 ~ 16mhz) symbol parameter min max unit test conditions v il input low voltage (p0) -0.3 0.8 v v il1 p1, p2, p3, p8 -0.3 0.3v cc v v il2 reset , int0, nmi -0.3 0.25v cc v v il3 ea -0.3 0.3 v v il4 x1 -0.3 0.2v cc v v ih input low voltage (d0 ~ d7) 2.2 v cc + 0.3 v v ih1 p3, p5, p6, p7, p8 0.7v cc v cc + 0.3 v v ih2 reset , int0, nmi 0.75v cc v cc + 0.3 v v ih4 x1 0.8v cc v cc + 0.3 v v ol output low voltage 0.45 v i ol = 1.6ma v oh v oh1 v oh2 output high voltage 2.4 0.75v cc 0.9v cc v v v i oh = -400 m a i oh = -100 m a i oh = -20 m a i dar darlington drive current (8 i/o pins) -1.0 -3.5 ma v ext = 1.5v r ext = 1.1k w i li input leakage current 0.02 (typ) 5 m a 0.0 vin v cc i lo output leakage current 0.05 (typ) 10 m a 0.2 vin v cc - 0.2 i cc operating current (run) idle 1 idle 2 17 (typ) 1.5 (typ) 6 (typ) 30 5 15 ma ma ma tosc = 10mhz (60% up @ 16.0mhz) stop (ta = -20 ~ 70 c) stop (ta = 0 ~ 50 c) 0.2 (typ) 50 10 m a m a 0.2 vin v cc - 0.2 v stop power down voltage (@stop) 2 ram back up 6k w v il2 = 0.2v cc , v ih2 = 0.8v cc r rst reset pull up register 50 150 k w cio pin capacitance 10 pf testfreq = 1mhz v th schmitt width reset , nmi , int0 0.4 1.0 (typ) v www.datasheet.in
10/14 toshiba corporation TMP90PH02 4.3 ac characteristics ac output level high 2.2v/low 0.8v ac input level high 2.4v/low 0.45v (d0 ?d7) high 0.8v cc /low 0.2v cc (excluding d0 ?d7) v cc = 5v 10% ta = -40 ~ 85 c (1 ~ 10mhz) cl = 50pf ta = -20 ~ 70 c (1 ~ 16mhz) symbol parameter variable 12.5mhz clock 16mhz clock unit min max min max min max t osc osc. period = x 62.5 1000 80 62.5 ns t cyc clk period 4x 4x 320 250 ns t wl clk low width 2x - 40 120 85 ns t wh clk high width 2x - 40 120 85 ns t ac address setup to rd , wr x - 45 35 18 ns t rr rd low width 2.5x - 40 160 117 ns t ca address hold time after rd , wr 0.5x - 30 20 12 ns t ad address to valid data in 3.5x - 95 185 123 ns t rd rd to valid data in 2.5x - 80 120 76 ns t hr input data hold after rd 0 0?ns t ww wr low width 2.5x - 40 160 117 ns t dw data setup to wr 2x - 50 110 75 ns t wd data hold after wr 20 70 20 70 20 70 ns t cwa rd , wr to valid wait 1.5x - 100 20 13 ns t awa address to valid wait 2.5x - 130 70 26 ns t was wait setup to clk 50 50 50 ns t wah wait hold after clk 0 0?ns t rv rd /wr recovery time 1.5x - 35 85 59 ns t cpw clk to port data output x + 200 280 262 ns t prc port data setup to clk 200 200 200 ns t cpr port data hold after clk 100 100 100 ns t chcl rd /wr hold after clk x - 40 40 23 ns t clc rd /wr setup to clk 1.5x - 25 95 69 ns t clha address hold after clk 1.5x - 80 40 14 ns t acl address setup to clk 2.5x - 80 120 77 ns t cld data setup to clk x - 50 30 13 ns www.datasheet.in
toshiba corporation 11/14 TMP90PH02 4.4 zero - cross characteristics v cc = 5v 10% ta = -40 ~ 85 c (1 ~ 10mhz) ta = -20 ~ 70 c (1 ~ 16mhz) symbol parameter condition min max unit v zx zero-cross detection input ac coupling c = 0.1 m f 1 1.8 vac p - p a zx zero-cross accuracy 50/60hz sine wave 135 mv f zx zero-cross detection input frequency 0.04 1 khz 4.5 serial channel timing - i/o interface mode v cc = 5v 10% ta = -40 ~ 85 c (1 ~ 10mhz) cl = 50pf ta = -20 ~ 70 c (1 ~ 16mhz) symbol parameter variable 10mhz clock 16mhz clock unit min max min max min max t scy serial port clock cycle time 8x 640 500 ns t oss output data setup sclk rising edge 6x - 150 330 225 ns t ohs output data hold after sclk rising edge 2x - 80 40 45 ns t hsr input data hold after sclk rising edge 0 0?ns t srd sclk rising edge to input data valid 6x - 150 330 225 ns 4.6 8-bit event counter v cc = 5v 10% ta = -40 ~ 85 c (1 ~ 10mhz) cl = 50pf ta = -20 ~ 70 c (1 ~ 16mhz) symbol parameter variable 10mhz clock 16mhz clock unit min max min max min max t vck ti2 clock cycle 8x + 100 740 600 ns t vckl ti2 low clock pulse width 4x + 40 360 290 ns t vckh ti2 high clock pulse width 4x + 40 360 290 ns 4.7 interrupt operation v cc = 5v 10% ta = -40 ~ 85 c (1 ~ 10mhz) cl = 50pf ta = -20 ~ 70 c (1 ~ 16mhz) symbol parameter variable 10mhz clock 16mhz clock unit min max min max min max t intal nmi , int0 low level pulse width 4x 320 250 ns t intah nmi , int0 high level pulse width 4x 320 250 ns t intbl int1, int2 low level pulse width 8x + 100 740 600 ns t intbh int1, int2 high level pulse width 8x + 100 740 600 ns www.datasheet.in
12/14 toshiba corporation TMP90PH02 4.8 read operation (prom mode) tcyc = 400ns (10mhz clock) a = 200ns 4.9 programming operation (prom mode) 4.10 i/o interface mode timing dc characteristic, ac characterisc ta = -40 ~ 85 c vcc = 5v 10% symbol parameter condition min max unit v pp v ih1 v il1 vpp read voltage input high voltage (a0 ~ a15, ce , oe ) input low voltage (a ~ a15, ce , oe ) 4.5 0.7 x v cc -0.3 5.5 vcc + 0.3 0.3 x v cc v v v t acc address to output delay c l = 50 p f 2.25tcyc + a ns dc characteristic, ac characteristic ta = 25 5 c vcc = 6v 0.25v symbol parameter condition min typ max unit v pp v ih v il v ih1 v il1 i cc i pp programming voltage input high voltage (d0 ~ d7) input low voltage (d0 ~ d7) input high voltage (a0 ~ a15, ce , oe ) input low voltage (a0 ~ a15, ce , oe ) v cc supply current v pp supply current f osc = 10mhz v pp = 13.00v 12.25 0.2v cc + 1.1 -0.3 0.7v cc -0.3 12.50 12.75 v cc + 0.3 0.2v cc - 0.1 v cc + 0.3 0.3v cc 50 50 v v v v v ma ma t pw ce programming pulse width c l = 50 p f 0.95 1.00 1.05 ms www.datasheet.in
toshiba corporation 13/14 TMP90PH02 4.11 timing chart 4.12 read operation timing chart (prom mode) www.datasheet.in
14/14 toshiba corporation TMP90PH02 4.13 programming operation timing chart (prom mode) www.datasheet.in

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